With the demand for higher levels of integration of semiconductor chips, such as silicon semiconductor chips, and the need for greater density in these circuits, the conductive line dimensions and spaces between the conductive lines of the integrated circuits become more and more critical. This is especially the case with a microprocessor integrated circuit chip of which a large portion of the real estate of the chip is an SRAM. For increased performance of future microprocessors, the storage capacity of the SRAM must increase thereby requiring a larger portion of real estate of the microprocessor.
A limit on the dimensions in the integrated circuits is the resolution of the optical lithographic system used in the fabrication of the integrated circuit including the conductive line levels. Today, with deep ultra violet photolithography, the resolution limit is about 0.25 microns. To break through this barrier, semiconductor manufactures are resorting to techniques like phase shift lithography, which require expensive masks but permit optical lithography to achieve these small line widths, and X-ray lithography which is extremely costly from an exposure equipment and mask making standpoint. Electron beam is another exposure alternative to achieve line widths of less than 0.25 microns, but its throughput is extremely slow when it is used in a direct write mode.
Techniques are thus required to reduce the line widths without resorting to expensive masks or exposure equipment and permit the use of conventional optical lithography.